Conventional polysilicon/silicon oxynitride (SiON) gate stacks have become increasingly unsuitable due to excessive gate leakage as the gate dielectric is proportionally thinned as gate length is decreased. The introduction of novel gate stack materials including high-K (HK) dielectric materials, and metal gates has enabled the continuation of Moore's Law with respect to transistor sizing at nodes smaller than 45/32 nm. However, different schemes to integrate those novel materials into gate stacks have been recently proposed. Gate-first (GF) and gate-last (GL), along with hybrid integration techniques that use some features of both gate-first and gate-last have all been described. The terminology ‘first’ and ‘last’ refers to whether the metal electrode is deposited before or after the high temperature activation anneal(s).
The gate-first approach relies on the use of very thin capping layers—aluminum (Al) based (e.g. Al2O3) for the PMOS and lanthanum (La) based (e.g. LaOx) for the NMOS transistors—to create dipoles that set a workfunction of the gate stack, defining its threshold voltage. In practice, systematic thermal instabilities of the HK/metal gate (MG) stacks can lead to significant workfunction shifts towards midgap (translating into higher PMOS threshold voltage (Vt)). This issue is particularly acute for PMOS, impeding use of gate-first stack construction in low Vt PMOS devices.
A second way of integrating HK/MG has been called a gate-last process. Typically, a sacrificial polysilicon gate is created over an already-formed hafnium-based dielectric gate oxide. The polysilicon gate forms the alignment for the high-temperature process steps such as the formation of source and drain regions in the substrate. After the high-temperature source-drain (S-D) and silicide annealing cycles, the dummy gate is removed and metal gate electrodes are deposited last. In an alternative process, the high-K dielectric itself can be deposited last, right before the metal gate electrodes, and after the complete removal of the dummy polysilicon gates. One possible advantage with this latter approach is to improve the device reliability and mobility at a scaled equivalent oxide thickness (EOT), which can be significantly degraded when the high-K dielectric has gone through the high thermal steps of the flow, just like in the gate-first approach. In both variations of a gate last flow (partial & full gate-last), the workfunction metals are not subjected to high thermal steps often associated with front-end flows.
Hybrid approaches to integrate HK/MG have been disclosed, combining both gate-first (for NMOS) and gate-last (for PMOS). Such hybrid approaches allow targeting high-performance system on a chip (SoC) die that include high PMOS Vt at scaled EOT, while avoiding the full, complex CMOS gate-last integration, that requires multiple CMP steps and dual metal gate deposition. However, both hybrid and gate-last process flows are very complex, with dual metal gates formation requiring costly and time consuming chemical mechanical polishing (CMP) steps. To maintain sufficient process window, such approaches may require restricted design rules (RDRs), such as use of 1-D design approach where gates are all aligned in a given direction.
In addition to the foregoing issues, available metal gate processing techniques for manufacture of low Vt devices required for SOC applications often require CMOS dual workfunction gate stacks. This complicates the HK/MG integration flow, whether gate-first, gate-last, or hybrid processing techniques are chosen. In a typical gate last flow, two metal gates are used, whereas in the case of gate-first, either two capping layers are needed (typically La-based for NMOS and Al-based for PMOS) or a single capping for NMOS (typically La-based) with a SiGe channel for PMOS. In such process flows, SiGe is used due to its valence band offset compared to silicon. Therefore, SiGe channels can deliver effectively lower Vt, in first order proportionally to its Ge content. However, the combination of these different materials and the structures required using these materials increase cost, process complexity, and device failure rates.